主機橋內部交錯¶
此 cxl-cli 配置轉儲顯示了以下主機配置
一個具有一個 CXL 根的單插槽系統
CXL 根有四 (4) 個 CXL 主機橋
一 (1) 個 CXL 主機橋連線了兩個 CXL 記憶體擴充套件器
主機橋解碼器被程式設計為在擴充套件器之間交錯。
此輸出由 cxl list -v 生成，並描述了在 /sys/bus/cxl/devices/ 中暴露的物件之間的關係。
[
{
"bus":"root0",
"provider":"ACPI.CXL",
"nr_dports":4,
"dports":[
{
"dport":"pci0000:00",
"alias":"ACPI0016:01",
"id":0
},
{
"dport":"pci0000:a8",
"alias":"ACPI0016:02",
"id":4
},
{
"dport":"pci0000:2a",
"alias":"ACPI0016:03",
"id":1
},
{
"dport":"pci0000:d2",
"alias":"ACPI0016:00",
"id":5
}
],
此段顯示 CXL“匯流排”（root0）有 4 個下游埠連線到 CXL 主機橋。根可以被視為連線到平臺記憶體控制器的單個上游埠，它將記憶體請求路由到該控制器。
ports:root0 部分說明了每個下游埠的配置方式。如果埠未配置（ID 為 0 和 1），則會省略它們。
"ports:root0":[
{
"port":"port1",
"host":"pci0000:d2",
"depth":1,
"nr_dports":3,
"dports":[
{
"dport":"0000:d2:01.1",
"alias":"device:02",
"id":0
},
{
"dport":"0000:d2:01.3",
"alias":"device:05",
"id":2
},
{
"dport":"0000:d2:07.1",
"alias":"device:0d",
"id":113
}
],
此段顯示了與 CXL 主機橋 port1 相關聯的可用下游埠。在此示例中，port1 有 3 個可用下游埠：dport1、dport2 和 dport113。
"endpoints:port1":[
{
"endpoint":"endpoint5",
"host":"mem0",
"parent_dport":"0000:d2:01.1",
"depth":2,
"memdev":{
"memdev":"mem0",
"ram_size":137438953472,
"serial":0,
"numa_node":0,
"host":"0000:d3:00.0"
},
"decoders:endpoint5":[
{
"decoder":"decoder5.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"dpa_resource":0,
"dpa_size":137438953472,
"mode":"ram"
}
]
},
{
"endpoint":"endpoint6",
"host":"mem1",
"parent_dport":"0000:d2:01.3,
"depth":2,
"memdev":{
"memdev":"mem1",
"ram_size":137438953472,
"serial":0,
"numa_node":0,
"host":"0000:a9:00.0"
},
"decoders:endpoint6":[
{
"decoder":"decoder6.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"dpa_resource":0,
"dpa_size":137438953472,
"mode":"ram"
}
]
}
],
此段顯示了連線到主機橋 port1 的端點。
endpoint5 包含一個已配置的解碼器 decoder5.0，它屬於相同的交錯配置記憶體區域（稍後顯示）。
接下來是屬於主機橋的解碼器
"decoders:port1":[
{
"decoder":"decoder1.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":2,
"interleave_granularity":256,
"region":"region0",
"nr_targets":2,
"targets":[
{
"target":"0000:d2:01.1",
"alias":"device:02",
"position":0,
"id":0
},
{
"target":"0000:d2:01.3",
"alias":"device:05",
"position":1,
"id":0
}
]
}
]
},
主機橋 port1 有一個單獨的解碼器 (decoder1.0)，具有兩個目標：dport1 和 dport3 — 它們分別連線到 endpoint5 和 endpoint6。
主機橋解碼器以 256 位元組的粒度交錯這些裝置。
下一段顯示了三個未連線端點的 CXL 主機橋。
{
"port":"port2",
"host":"pci0000:00",
"depth":1,
"nr_dports":2,
"dports":[
{
"dport":"0000:00:01.3",
"alias":"device:55",
"id":2
},
{
"dport":"0000:00:07.1",
"alias":"device:5d",
"id":113
}
]
},
{
"port":"port3",
"host":"pci0000:a8",
"depth":1,
"nr_dports":1,
"dports":[
{
"dport":"0000:a8:01.1",
"alias":"device:c3",
"id":0
}
],
},
{
"port":"port4",
"host":"pci0000:2a",
"depth":1,
"nr_dports":1,
"dports":[
{
"dport":"0000:2a:01.1",
"alias":"device:d0",
"id":0
}
]
}
],
接下來是屬於 root0 的 根解碼器。此根解碼器以 256 位元組的粒度在下游埠 port1 和 port3 之間應用交錯。
此資訊由 CXL 驅動程式讀取 ACPI CEDT CMFWS 生成。
"decoders:root0":[
{
"decoder":"decoder0.0",
"resource":825975898112,
"size":274877906944,
"interleave_ways":1,
"max_available_extent":0,
"volatile_capable":true,
"nr_targets":2,
"targets":[
{
"target":"pci0000:a8",
"alias":"ACPI0016:02",
"position":1,
"id":4
},
],
最後，我們有與 根解碼器 decoder0.0 相關聯的 記憶體區域。此區域描述了交錯集的整體交錯配置。
"regions:decoder0.0":[
{
"region":"region0",
"resource":825975898112,
"size":274877906944,
"type":"ram",
"interleave_ways":2,
"interleave_granularity":256,
"decode_state":"commit",
"mappings":[
{
"position":1,
"memdev":"mem1",
"decoder":"decoder6.0"
},
{
"position":0,
"memdev":"mem0",
"decoder":"decoder5.0"
}
]
}
]
}
]
}
]